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<title>CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers </title></head>
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<h1>CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>
<p>66 0F 2C /<em>r</em></p>
<p>CVTTPD2PI <em>mm</em>, <em>xmm/m128</em></p></td>
<td>RM</td>
<td>Valid</td>
<td>Valid</td>
<td>Convert two packer double-precision floating-point values from <em>xmm/m128</em> to two packed signed doubleword integers in <em>mm</em> using truncation.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register.</p>
<p>When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.</p>
<p>This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.</p>
<p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
<h2>Operation</h2>
<pre>DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32_
                    Truncate(SRC[127:64]);</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>CVTTPD1PI:</p>
<p> __m64 _mm_cvttpd_pi32(__m128d a)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Invalid, Precision</p>
<h2>Other Mode Exceptions</h2>
<p>See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-ment,” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B</em>.</p></body></html>